From CoWoS to CoPoS: TSMC launches an "advanced packaging revolution" sweeping through the chip industry chain.

Recently, Wall Street financial giant Morgan Stanley released a research report stating that Taiwan Semiconductor Manufacturing Co., Ltd. Sponsored ADR (TSM.US), known as the "king of chip manufacturing," has started construction of a 310 mm Panel-Level chiplet advanced packaging pilot line (CoPoS advanced packaging system), and has prompted companies like ASE and other semiconductor equipment and advanced packaging equipment giants to reduce the FOPLP size to 300/310 mm. This signifies that the packaging super update iteration from wafer-level CoWoS to panel-level CoPoS advanced packaging has officially entered the investment and initial trial production phase. The launch of the CoPoS pilot line by Taiwan Semiconductor Manufacturing Co., Ltd. Sponsored ADR indicates that this chip manufacturing giant is officially leading a "major transformation of advanced packaging" covering the entire chip industry chain from upstream to downstream. CoPoS will mainly be used to solve the capacity bottleneck of the CoWoS advanced packaging on a large scale, as well as address the cost issues related to initial wafer flow and the entire manufacturing to packaging process. It is aimed at next-generation AI training/inference AI GPU/AI ASIC, seeking to achieve exponential performance improvement by encapsulating chiplets on a larger scale and increasing the HBM stack, with the potential to reduce the cost of expanding capacity compared to CoWoS. Global chip industry chain research data from Morgan Stanley shows that Taiwan Semiconductor Manufacturing Co., Ltd. Sponsored ADR has invested in the construction of a CoPoS 310 mm pilot line, with ASE almost simultaneously releasing a 2.3D packaging technology (FOCoS-Bridge) using a 300 mm panel, indicating a rapid transition to 310 mm in the advanced packaging industry. In June 2025, the Japan Institute of Electronics Packaging (JIEP) seminar also featured a large number of semiconductor equipment and materials exhibits related to PLP/CoPoS. The industry is expected to see a large-scale delivery and installation of CoPoS-related semiconductor equipment in mid-2026, process initiation in 2027, a significant investment decision period in 2027, and initial wafer flow. The CoPoS advanced packaging system draws on the silicon stacking technology of CoWoS, but has made systematic adjustments in terms of substrate form, high-end semiconductor equipment chain, and yield bottleneck, with stronger performance ceilings and more expandable capacity, meeting the increasingly large global demand for AI computing power. For NVIDIA Corporation, AMD, Broadcom Inc., Marvell Technology, Inc., and other AI/HPC super clients, CoPoS offers larger-scale advanced packaging I/O and HBM stack numbers, greatly alleviating the supply-demand imbalance and high initial wafer flow and chip manufacturing costs in advanced packaging. From a "performance limit" perspective, the combination of the panel-level area and HBM stack in CoPoS can provide a larger bandwidth/capacity expansion compared to the current CoWoS advanced packaging, giving AI chips focused on large model training/inference systems a higher performance ceiling. From the perspective of revenue growth and valuation expansion, the entire chip industry chain is expected to experience significant growth. For NVIDIA Corporation, AMD, and the three major EDA giants, there is potential to drive larger terminal demand through product updates and iterations on the supply side, especially for AI chip leader NVIDIA Corporation, which is expected to more fully meet the "vast" AI computing power demand; the semiconductor high-end equipment and chip material chain, with the move towards panelization in CoPoS, is about to usher in a new round of large-scale equipment capital expenditure, especially for the world's top semiconductor equipment manufacturers in areas such as laser cutting, panel lithography, vacuum bonding, and dry film packaging, where key equipment includes Panel-level direct writing lithography, laser cutting, and panel bonding. From wafer to panel: Taiwan Semiconductor Manufacturing Co., Ltd. Sponsored ADR leads the "CoPoS revolution" The CoWoS (Chip-on-Wafer-on-Substrate) advanced packaging process focuses on completing the redistribution layer (RDL) and TSV on the silicon interposer on a 300mm wafer, then mounting the logic/storage chips on it, and finally bonding it to the BT/ABF organic substrate. Due to the limited effective area of the wafer, after accommodating large core chips and multiple HBM slots, the yield decreases with the area, ultimately leading to high cost per chip, long-term capacity constraints, and reaching a performance ceiling. The CoPoS (Chip-on-Panel-on-Substrate) process focuses on moving the silicon interposer or redistribution layer to a rectangular panel (PLP) (typically 310 mm 310 mm), first creating a large-area embedded silicon RDL, then mounting core chiplet chips/HBM, and finally assembling them with organic substrate. CoPoS aims to encapsulate more chiplet chips and higher HBM stack numbers in one pass, aimed at the performance leap in the next-generation AI chips and below 1nm advanced processes. However, challenges such as warping and uniformity of edge coatings have emerged. Therefore, based on the high panel utilization of CoPoS, a single panel area is approximately 3-5 times that of a wafer, potential capacity improvement 2-3, and a 20-30% reduction in unit area cost, the semiconductor equipment chain may need to be re-adapted (mainly focused on large laser cutting, direct imaging lithography, and vacuum bonding machines). Morgan Stanley says that for the chip industry chain, transitioning from 12-inch wafer-level equipment to PLP-related materials and equipment is a new round of large-scale CAPEX cycle, with semiconductor equipment giants (such as Disco, Ulvac, Screen HD, and Canon) expected to receive incremental orders, representing a significant structural growth opportunity. CoPoS and AI Computing Power With the global popularity of ChatGPT and the emergence of large-scale models like Sora for video creation, combined with NVIDIA Corporation's unparalleled performance in the AI chip market, it signifies that society has entered the AI era. At the end of May's NVIDIA Corporation earnings call, Jensen Huang was extremely optimistic about the Blackwell series setting a record for the most powerful AI chip sales, driving the artificial intelligence computing power infrastructure market to show "exponential growth". "Now, every country views AI as the core of the next industrial revolution - an emerging industry that continuously produces intelligence and critical infrastructure for every economy in the world," Jensen Huang said in discussions with analysts. The demand for AI computing power brought about by inference is expected to drive continuous exponential growth in the artificial intelligence computing power infrastructure market. Huang also believes that the "AI inference system" will be NVIDIA Corporation's largest revenue source in the future. In the unprecedented competition for AI infrastructure in the current era, CoWoS at the wafer level has pushed NVIDIA Corporation's AI GPU advanced packaging to at least 6 HBM storage systems with a total bandwidth of 3.9 - 4.8 TB/s, with CoWoS-S limited by the size of the silicon interposer within 120 150 mm. On the other hand, the panel-level CoPoS, by enlarging the carrying area to a typical 310 310 mm, can accommodate up to 10-12 next-generation HBMs - HBM4 and more chiplet chips, with a theoretical peak bandwidth expected to exceed 13-15 TB/s, doubling the storage capacity. A larger panel size allows for greater integration of GPU/CPU chiplets, optical I/O Dies, and dedicated AI acceleration IP, significantly reducing overall latency and power consumption through exponential interconnection. Therefore, in terms of next-generation AI chip performance and meeting computing power demands, CoPoS offers a much broader "performance ceiling" and better meets the computing power requirements. This means that as the demand for AI computing power and the scale of AI models continue to explosively grow, even as the HBM stack reaches more than 10 chips, CoPoS advanced packaging will fully leverage its panel area advantage, bringing about larger-scale improvements in the performance of AI chips and infrastructure at a lower cost per unit of computing power. For example, when the available area on a CoPoS panel exceeds five times that of a single CoWoS wafer, and with the use of HBM4 (1.6 TB/s per stack, 2,048-bit bus), 12 stacks can achieve a peak bandwidth of over 19 TB/s - a more than four times increase in the bandwidth limit compared to current CoWoS technology.