CITIC SEC: Tao's Law Advances Product Validation, Focusing on Opportunities in the Logic Folding Industry Chain

CITIC SEC has published a research report stating that the Tao Law has transitioned from a theoretical framework to product development. On September 4, He Tingbo, the head of Huawei's semiconductor division, released a follow-up paper on Tao Law, focusing on the power consumption and heat dissipation issues of 3D stacked chips. On September 7, Huawei launched the Mate XT2 ULTIMATE DESIGN, which is the first to feature the Kirin 9050 Pro, achieving over 42% improvement in overall performance compared to the previous generation. The firm believes the Kirin 9050 Pro has become the first product validation window for the Tao Law. Logic Folding will increase the demand for multilayer active wafer manufacturing and wafer-level hybrid bonding, driving upgrades in CMP, cleaning, deposition, etching, measurement, and testing processes. It is recommended to pay close attention to the domestic wafer manufacturing, semiconductor equipment, and testing industry chains. CITIC SEC's main points are as follows: Event: Huawei releases a follow-up paper on Tao Law and the Mate XT2 featuring the Kirin 9050 Pro. On September 4, He Tingbo released the paper "Huaweis Chip Was Supposed to Melt?" This is the third publication or update regarding the Tao Law in less than four months, following papers released on May 25 and July 3, with a focus on addressing power consumption and heat dissipation issues of 3D stacked chips. On September 7, Huawei launched the Mate XT2 ULTIMATE DESIGN, the first to feature the Kirin 9050 Pro, with an overall performance improvement of over 42% compared to the Mate XTs. The firm believes the Tao Law has transitioned from theoretical validation to terminal product stage. The September paper further explains the underlying mechanisms of Logic Folding in improving power consumption and heat dissipation. The paper points out that in typical smartphone workloads, dynamic power consumption accounts for about 90% of total power consumption. Besides the switching of transistors, signal transmission in metal interconnections is also a major source of energy consumption. Logic Folding transforms long-distance horizontal interconnections into short-distance vertical interconnections, shortening the folding path length of typical cores by about 20%, with some critical paths reduced by up to 70%, thus reducing interconnection capacitance and dynamic power consumption. When considering equal performance modes, the NPU, GPU, and CPU power consumption of the Kirin 2026's performance cores decreased by 66%, 58%, and 41% compared to the previous generation, while transistor density improved by 55%, preliminarily validating that Logic Folding can balance the enhancement of transistor density with energy efficiency. The Kirin 9050 Pro demonstrates comprehensive performance improvements, becoming an important product validation window for the Tao Law. According to Huawei's press conference, the Kirin 9050 Pro features a nine-core Lingxi CPU, with single-core peak performance and multi-core concurrency performance improved by over 24% and 52%, respectively; the Maliang GPU has doubled the number of computing units and the cache capacity, achieving more than a 142% increase in rendering performance; the Da Vinci architecture NPU supports a total of 30 billion parameters and 2 billion active parameters for side MoE large models. Additionally, the Mate XT2 sees improvements of over 50%, 35%, and 40% in large file opening speed, multitasking smoothness, and 4K video export speeds, respectively. The firm believes that the multi-core parallelism of the CPU, the expansion of the GPU computing units, and the implementation of large models on the side align with the Tao Law's aim of reducing task time by increasing parallelism. Chip packaging and system-level heat dissipation are cooperatively upgraded, with preliminary responses to the 3D stacked heat dissipation issues. The Kirin 9050 Pro features a multi-channel thermal conductive package, while the Mate XT2 utilizes a super-large VC and a graphene cross-axis cooling system, collectively reducing temperature rise during gaming by 2.5C. The paper suggests controlling power density and localized hotspots through reduced interconnection power consumption, selective folding, interlaced layout of hot and cold modules, and thermal-aware design. The firm believes the chip's measured data in the paper correspond with the disclosed improvements in system heat dissipation of the new products, indicating that the validation of the Tao Law is extending from transistor density and performance to power consumption and heat dissipation. Hybrid bonding continues to miniaturize, expected to enhance the value of wafer manufacturing and equipment. The paper shows that the hybrid bonding pitch of the Kirin 2026 has reached 1.5 m, with the number of vertical interconnections reaching 50 million; the Kirin 2027 has further reduced the pitch to 1 m, exceeding 100 million vertical interconnections, with future goals aiming for 720 nm and over 200 million interconnections in the next three years, and a long-term target of 480 nm. As Logic Folding gradually materializes, the firm anticipates increases in multilayer active wafer investments and wafer-level hybrid bonding processes, driving higher demand for CMP, cleaning, deposition, etching, alignment, measurement, and multi-stage testing. Risk factors: Downstream AI and terminal demand may fall short of expectations; capacity expansion of domestic wafer fabs and the domestic substitution process may not meet expectations; expansion could lead to intensified competition; geopolitical tensions and trade frictions may escalate. Investment strategy: Focus on the wafer manufacturing, semiconductor equipment, and testing industry chains. In the follow-up, the firm suggests closely monitoring the Kirin 9050 Pro's measured performance and power consumption, as well as the industrialization progress of Logic Folding and wafer-level hybrid bonding.