Sinolink: CoWoS enters a new stage, SIC is expected to enter the period of industrial production volume.

Sinolink released a research report stating that Taiwan Semiconductor Manufacturing Co., Ltd. Sponsored ADR (TSM.US) plans to introduce a transitional version with a mask size 5.5 times larger in 2026, and achieve mass production of a CoWoS with a mask size 9.5 times larger in 2027, in order to accurately match the exponential demand for memory capacity and interconnect bandwidth of AI large models. SiC, with its characteristics of high thermal conductivity, high rigidity, CTE, and matching with silicon chip, has become a key material to break through the dual bottleneck of thermal and mechanical issues in CoWoS. It is expected to gradually introduce SiC into CoWoS as thermal diffusion layer, thermal bearing layer, and structural support layer, fully utilizing the material's advantages and reducing the difficulty of process adaptation. Sinolink's main points are as follows: CoWoS enters a new stage of large size, high HBM, and high heat flux density TSMC clarified the next generation CoWoS evolution direction at the North American Technology Forum in April 2025, establishing large size, high HBM stacking, and high heat flux density as the advanced packaging core. The company plans to introduce a transitional version with a mask size 5.5 times larger in 2026, and achieve mass production of CoWoS with a mask size 9.5 times larger in 2027, with a single package effective area close to 8,000mm, supporting the integration of 4 3D stacked chip systems, 12 layers and above HBM, and multiple logic chip high-density integration, accurately matching the exponential demand for memory capacity and interconnect bandwidth of AI large models. The simultaneous introduction of the SoWX wafer-level system integration solution can achieve computing power 40 times that of the current CoWoS, and is scheduled to be mass-produced in 2027. This roadmap is highly consistent with the next generation AI chip planning of NVIDIA. Products like RubinUltra adopt CoWoSL packaging and N3P process, demonstrating that large size, high bandwidth, and high power density have become the core competitive dimensions of high-end packaging in the next 2-3 years. Advanced packaging has evolved from a supporting link to a key variable determining the upper limit of AI computing power. CoWoS bottleneck shifts to thermal management and warpage control, with thermal-mechanical coupling as a core production constraint With the iteration of CoWoS to ultra-large size, the industry's core contradiction has shifted from production capacity constraints to thermal management and warpage control. TSMC's 110x110mm CoWoSR solution can integrate 4 SoCs + 12 HBMs, significantly increasing integration and computing power levels, but ECTC 2025 clearly points out that warpage control has become an urgent challenge. In ultra-large size packaging, the mismatch of thermal expansion coefficients between chips, intermediate layers, and substrates exacerbates issues such as severe warpage, open circuits, solder ball cracking, and interlayer delamination that can result from reflow soldering and high-low temperature cycling. High-end AI packaging with high integration features, with damage to a single HBM or logic chip leading to the scrapping of the entire chip, fluctuations in yield result in significant cost losses. Thermal resistance control, warpage suppression, and assembly yield become key bottlenecks for mass production. The industry's competitive logic has shifted from performance metrics to system-level solutions competition, benefiting deeply from links with low thermal resistance materials, low warpage substrates, high-precision assembly equipment, and stress simulation capabilities. SiC Material advantages standout, entering advanced packaging bottleneck breakthrough from non-core layer of thermal management SiC, with its characteristics of high thermal conductivity, high rigidity, CTE, and matching with silicon chips, has become a key material to solve the dual bottleneck of thermal and mechanical issues in CoWoS. The thermal conductivity of 4HSiC reaches 370490W/mK, much higher than traditional silicon intermediate layers and organic RDL substrates, while also possessing high Young's modulus, low thermal expansion coefficient, and high temperature stability, allowing for the construction of a low thermal resistance, high rigidity, stress-adapted structure between chip and intermediate layer substrates. In applications with power levels in the thousands of watts and local hotspots exceeding 150C, SiC can quickly homogenize heat, suppress warpage deformation, and improve assembly yield and long-term reliability. SiC is expected to gradually enter CoWoS as a thermal diffusion layer, thermal bearing layer, and structural support layer, fully leveraging the advantages of the material and reducing the difficulty of process adaptation. Related targets SICC Co.,Ltd. (02631), Crystal Growth & Energy Equipment Inc. (688478.SH), Hunan Yujing Machinery (002943.SZ), Yangzhou Yangjie Electronic Technology (300373.SZ), China Resources Microelectronics (688396.SH), Sanan Optoelectronics (600703.SH), etc. Risk warning The risk of SiC introduction into advanced packaging progress falling short of expectations; the risk of high cost of SiC materials and limited scale applications; the risk of changes in advanced packaging technology roadmap; the risk of lower-than-expected yield and reliability verification of SiC in the packaging process.