Northeast: Computing power supply architecture upgrade; tertiary power supplies see both volume and price increases and a window for domestic substitution

date
10:18 30/10/2026
avatar
GMT Eight
VPD shortens the power delivery path, and the layout beneath the processor is becoming more compact, driving capacitors to upgrade toward low parasitic parameters, thinness, and substrate embedding.
Northeast released a research report stating that architecture upgrades are driving coordinated development of power stages, magnetic components, decoupling capacitors, and PCBs. Suppliers with high-density integration and system adaptation capabilities are expected to benefit. Attention should be paid to the incremental demand for core components and domestic import opportunities brought by VPD architecture upgrades. Northeast's main viewpoints are as follows: VPD: Verticalization of the power delivery path opens up near-proximity power supply upgrades for AI chips AI chip power and supply current continue to increase, and traditional lateral power delivery faces transmission losses, transient voltage drops, and board space constraints. VPD moves the final-stage power module beneath the processor, shortening the low-voltage high-current path, reducing distribution losses, and freeing up routing space around the chip. It is expected to evolve toward integration into the motherboard and package substrate. Architecture upgrades are driving coordinated development of power stages, magnetic components, decoupling capacitors, and PCBs. Suppliers with high-density integration and system adaptation capabilities are expected to benefit. Attention should be paid to the incremental demand for core components and domestic import opportunities brought by VPD architecture upgrades. DrMOS: Coordinated upgrades of high current and high power density, with domestic manufacturers accelerating breakthroughs DrMOS integrates a driver and high-side/low-side MOSFETs and is the core power device for multiphase step-down power delivery. Increasing chip power is driving growth in power supply phases and device demand, and VPD further raises requirements for conversion efficiency, package height, and thermal performance. According to the firm's estimates, the global market for DrMOS used in data center AI chips is expected to exceed RMB45 billion by 2030 (subject to the preset estimation conditions in the main text). The high-end server segment remains dominated by international manufacturers, while domestic manufacturers such as Shanghai Bright Power Semiconductor Co., Ltd. and JoulWatt Technology are accumulating customer validation and volume supply capabilities through high-current power stages and multiphase controller matching. Inductors: VPD drives integrated upgrades of magnetic components, and TLVR penetration expands value space Vertical power delivery concentrates power modules beneath the processor, imposing higher requirements on inductor thinness, current-carrying capacity, and transient response, driving products from traditional discrete designs toward multiphase integration and TLVR solutions. Inductor usage typically matches the number of power supply phases, and AI chip power growth provides demand support; TLVR accelerates current response through cross-phase coupling, reducing the output capacitance required to meet equivalent transient specifications and adapting to high-density power delivery needs within VPD's limited space. According to the firm's estimates, the global market for TLVR inductors used in AI chip power delivery is expected to exceed RMB35 billion by 2030 (subject to the preset estimation conditions in the main text). Manufacturers such as POCO Holding and Shenzhen Sunlord Electronics are accelerating product validation and volume delivery by leveraging magnetic materials, precision manufacturing, or multiphase integration capabilities. High-frequency capacitors: Decoupling migrates closer to the chip, and silicon capacitors are expected to see in-package incremental demand VPD shortens the power delivery path, and layout beneath the processor becomes more compact, driving capacitors toward low parasitic parameters, thinness, and substrate embedding. Low-ESL MLCCs and silicon capacitors are expected to form a division of labor, with silicon capacitors expanding application space within advanced packaging by virtue of their three-dimensional structure, high capacitance density, and packaging adaptability. According to the firm's estimates, the global market for silicon capacitors used in AI chips is expected to exceed RMB20 billion by 2030 (subject to the preset estimation conditions in the main text). Manufacturers with accumulated device process and customer validation experience are expected to occupy a first-mover position. Risk warnings: Capital expenditure falling short of expectations, product implementation progress falling short of expectations, customer validation and domestic substitution progress falling short of expectations, and risks of market competition and declining profitability.