Micron (MU.US) Technology Symposium Lays Out Roadmap: Abandoning 4F, HBM4 Mass Production, G11 NAND Speedup... JP Morgan Maintains "Overweight" Rating

J.P. Morgan's latest research report notes that Micron Technology, Inc. (MU.US) detailed its latest technological innovations and long-term plans across its three core product linesDRAM, HBM, and NANDat its investor technology webinar held on October 21. The analyst team led by Harlan Sur believes that Micron's technology roadmap is clear and forward-looking, and that the company is poised to continue benefiting from the AI-driven explosion in memory demand, and therefore maintains its "Overweight" rating. Sticking with 6F DRAM Architecture, Pursuing 3D DRAM in Parallel J.P. Morgan notes in the report that regarding DRAM architecture evolution, Micron explicitly addressed the industry debate over 6F versus 4F technology routes. Micron stated that its next-generation DRAM nodes will continue to use the 6F architecture rather than 4F. The company is confident in maintaining its leadership in power and performance through rigorous node scaling, process innovation, and product-level optimization. Micron revealed that it has conducted research on 4F DRAM for about 20 years but ultimately decided not to adopt it, mainly because the architecture increases process complexity and cost, and the company believes its scaling benefits are limited. J.P. Morgan's report details three major manufacturing challenges facing the 4F architecture: First, the architecture requires denser deposition and etch processes, significantly increasing the probability of yield issues; second, 4F has more stringent process tolerance requirements (such as overlay and alignment), putting greater pressure on manufacturability and yield; finally, the architecture itself is prone to the "Floating Body Effect," causing charge to be trapped in the transistor channel, leading to performance degradation and leakage issues. In addition, Micron rebutted the view that 4F is superior to 6F in density, emphasizing that DRAM bit density is ultimately determined by capacitor pitch, not the underlying interconnect pitch. According to the currently disclosed roadmap, Micron will continue to utilize 6F-based planar architectures in its next several DRAM nodes (expected to extend through 2030), while developing 3D DRAM technology in parallel. HBM Roadmap Broadens Comprehensively, Customization and Vertical Stacking in Focus In the closely watched HBM space, Micron stated that HBM4 has now entered mass production, with ramp-up progressing smoothly, and the next-generation HBM4E is already on the roadmap, with the company sampling it to key customers this year. Looking ahead, Micron expects standard HBM and custom HBM to coexist over the long term. Custom HBM, by integrating memory IP and logic IP into the base die, enables deeper customer co-design. The Micron team noted that both future standard JEDEC HBM and custom HBM products will use foundry nodes, with HBM4E requiring more advanced CMOS processes due to higher requirements for speed, power, and functionality. In addition to standard and custom HBM, Micron also highlighted two important long-term memory architectures: Vertical HBM and vertical Edge Inference Memory (vEIM). Vertical HBM shortens the path between memory and compute by placing memory directly above the processor, thereby delivering significantly higher bandwidth; vEIM uses a similar approach but is specifically optimized for low-power edge AI inference use cases (i.e., Vertical HBM focuses on high bandwidth, while vEIM focuses on low power). Micron emphasized the growing importance of hybrid bonding, higher stacking layers, advanced thermal management, and customer co-design in the HBM roadmap. However, as HBM, Vertical HBM, and vEIM advance, these products will consume more wafers relative to standard DRAM output, meaning the wafer-to-bit output conversion ratio will remain under pressure. NAND Leaps Generations to G11, AI-Class Products Expand Market Opportunity In the NAND space, after three consecutive leading nodes from G7 to G9, Micron will leap directly to the G11 node optimized for AI workloads. Compared with G9, G11 aims to achieve approximately 2x bit density, up to 1.5x I/O speed improvement, and more than 25% reduction in energy per bit of data transfer, with stacking layers exceeding 400. The G11 node also marks Micron's formal introduction of Wafer-on-Wafer bonding technology in NAND manufacturing. The company expects G11 to ramp in the second half of 2027 and plans to disclose more details next year. In addition, Micron plans to continue scaling beyond G11 through new materials and higher-density cell architectures. At the product level, Micron is building two AI-class NAND products: one is a high-speed SLC-based design (offering 25 million to 100 million IOPS), specifically designed for GPUs to fetch massive small data blocks in tasks such as vector search and AI context retrieval; the other stacks NAND dies on a logic chip via TSV, thereby placing model weights, long context, and KV cache closer to the accelerator (not directly next to the GPU, as Micron believes there is no benefit in doing so). Given the higher cost, Micron is co-developing the second product with customers, and the market share of the two products is expected to vary by end market. In data center SSDs, Micron is already the first manufacturer to mass-produce PCIe Gen6 SSDs and ship 245TB drives, and the lower cost per bit from its advanced nodes is expected to support further growth in high-capacity drives. J.P. Morgan believes that Micron's NAND roadmap positions it to fully benefit from AI-driven memory demand growth and to maintain or expand its position among the global top three enterprise SSD (eSSD) market share holders. Deepening Customer Collaboration and Long-Cycle R&D, AI Tools Significantly Boost Efficiency Micron elaborated on a major shift in its customer engagement model. Compared with three to four years ago, collaboration now begins at the concept stage and runs through co-design, qualification, and mass production, including custom projects with multiple cloud service providers (CSPs). For example, Micron is customizing LPDDR6 for Meta (META.US) for data center deployment; and Weka has evolved from a Micron Ventures portfolio company into a commercial partner. On the R&D front, Micron's long-term investments span three time horizons: first, a commitment to invest $550 million in Micron Ventures over 3 to 10 years; second, a 5-to-10-year collaboration with Albany NanoTech/NY CREATES to develop a High-NA EUV and lithography roadmap for DRAM; and third, the $10 billion Micron Research Lab announced this summer, with a horizon of more than 10 years. In addition, Micron is deploying AI technology across its entire development cycle, from early research to fab operations. Data shows that on its latest data center SSD controller, AI-assisted chip design and verification cut tape-out time by half compared with the previous generation; AI-generated firmware, root cause analysis, and intelligent test selection shortened the path to customer-ready silicon for data center SSDs by 60%. Micron's goal is to accelerate the path from innovation to high-volume manufacturing (HVM) by 2x, and it is deepening cooperation with suppliers in areas such as lithography, packaging/hybrid bonding, and thin-film processing. J.P. Morgan believes these efforts are critical to Micron's ability to pursue more projects in parallel.