DeepSeek and Huawei Join Forces to Build CUDA Alternative

Chinese artificial intelligence enterprise DeepSeek has partnered with Huawei Technologies to build specialized programming tools optimized for Huawei’s Ascend processors, marking the latest endeavor by domestic technology firms to establish viable alternatives to Nvidia’s dominant ecosystem. In an official post on its WeChat account, DeepSeek announced that it is open-sourcing programming infrastructure for the Ascend platform, encompassing both computation and communication software libraries. This initiative was unveiled two weeks after Huawei introduced its next-generation artificial intelligence chips and supernode computing architectures, which are expected to be broadly utilized for AI model training in the coming year. DeepSeek stated that Huawei offered comprehensive assistance during development, enabling both organizations to jointly engineer a supernode solution powered by 128 Ascend 950 chips that streamlines computational throughput alongside communication efficiency.

Central to this technological collaboration is TileLang, an open-source, high-level programming language engineered for AI accelerators to elevate development productivity and simplify underlying code logic. DeepSeek emphasized that constructing an independent, self-controlled GPU software ecosystem requires prioritizing a universal, easily programmable high-level language capable of unlocking full hardware performance. According to the firm, TileLang was created specifically to fulfill this requirement, providing developers with a significantly simpler programming framework compared to Nvidia’s proprietary CUDA platform.

Concurrently, prominent Chinese dynamic random-access memory (DRAM) manufacturer ChangXin Memory Technologies (CXMT) announced plans to reallocate 18 billion yuan ($2.68 billion) in excess proceeds from its initial public offering toward two major strategic endeavors. Chinese market experts noted that this deployment underscores CXMT’s commitment to accelerating research and development while strengthening internal testing capabilities to support product diversification and deeper industrial chain integration. According to an official corporate filing released on Monday, CXMT will invest 13 billion yuan of its surplus IPO capital into a comprehensive technology R&D project with an overall cost of 24.1 billion yuan and a 30-month construction timeline. Focused on process and product development, this project aims to speed up generational advancements in DRAM architecture, helping CXMT adapt to shifting technological paradigms and fulfill downstream commercial demand.

Additionally, CXMT will direct 5 billion yuan through capital injections and shareholder loans to its wholly owned subsidiary, ChangXin Storage Products (Hefei) Co., to establish a second-phase storage wafer backend testing facility. Recognizing that backend testing is a specialized yet essential step in memory production, CXMT explained that surging output volumes and expanding product lines could create operational bottlenecks if reliant on third-party packaging vendors or constrained by insufficient external supplier investments. Establishing proprietary testing operations aims to prevent production delays, fortify supply chain resilience, lower overall testing expenses, increase operational efficiency, and further reinforce the company's integrated device manufacturer (IDM) framework. As of June 30, 2026, CXMT reported holding 4,484 domestic patents alongside 3,400 international patents, while employing 7,491 R&D staff members who account for more than 33 percent of its overall workforce. Furthermore, the memory maker has already achieved mass production on its fifth-generation process technology platform, with product offerings spanning DDR5, LPDDR5/5X, and LPDDR6 memory specifications.