CITIC SEC: Ascend 960 release moved up; the entire domestic computing power industry chain will benefit.
Huawei's 2026 Connect Conference shows that domestic computing power has escalated from "single-card" competition to full-stack competition based on "system-level solutions," and the entire domestic computing power industry chain will benefit.
CITIC SEC released a research report stating that Huawei's 2026 Connect Conference shows that domestic computing power has escalated from "single-card" to full-stack competition based on "system-level solutions." The entire domestic computing power industry chain will benefit, from scarce advanced process capabilities, to a flourishing array of design companies, and further to super nodes, all of which will see volume growth opportunities. At the same time, advanced processes, advanced packaging, advanced storage, and the supporting industry chain are expected to usher in strong growth momentum. Recommendations: 1) AI chip design companies. 2) Upstream supply chain. 3) Others.
CITIC SEC's main views are as follows:
Huawei's Ascend 960 series chip development exceeded expectations and will be released ahead of schedule.
On September 17, 2026, according to the Zhidongxi WeChat public account, Huawei announced at the 2026 Connect Conference that the development of the Ascend 960 series chips exceeded expectations and will be released ahead of schedule. Among them, Ascend 960DT will be released in 2027Q1, three quarters earlier than previously planned, and Ascend 960PR will be released in 2027Q3, one quarter earlier than previously planned. Ascend 960DT will support 2 PFLOPS (FP8) and 4 PFLOPS (FP4) computing power, achieving doubled performance compared with the previous generation, with maximum memory capacity support of 288GB, maximum memory bandwidth support of 9.6TB/s, and interconnect bandwidth support of 2.2TB/s. Huawei's better-than-expected Ascend 960 development indicates that the iteration of domestic computing power chips is developing rapidly under the drive of architecture design, and the capabilities of the domestic supply chain continue to improve.
Huawei launched the industry's first mass-produced NPO optical engine and the first super node using NPO, the Ascend 960 super node.
According to the Zhidongxi WeChat public account, at this conference Huawei launched the industry's first mass-produced NPO optical engine, Hi-ONE, as well as the industry's first super node using NPO, the Ascend 960 super node. A single Ascend 960 super node can achieve a scale of 4,096 cards, provide up to 8 EFLOPS FP8 computing power, and achieve up to 1PB of HBM capacity. At this conference, Huawei revealed that more than 1,000 Ascend 910C super nodes have been deployed, and Ascend 950 super nodes have already begun large-scale commercial use. As the parameter scale of large models increases beyond the 10T level, super nodes will become the core competitive product form for domestic computing power in the next stage, and the commercial implementation of optical interconnect will expand the application scale of super nodes.
Lingqu UnifiedBus drives MFU of 100,000-card clusters from 20% to 35%.
According to the Zhidongxi WeChat public account, the capabilities of Huawei's unified interconnect bus protocol for its computing power foundation, Lingqu UnifiedBus, have been further deepened. At this conference, Huawei stated that a single cluster based on Lingqu UnifiedBus can support 1 million AI processors, and the model floating-point utilization (MFU) of a 100,000-card cluster has increased from 20% to 35%. Huawei released 11 key chips for super node clusters based on Lingqu UnifiedBus, including computing, interconnect, and storage chips as well as various management function chip sets; in addition, based on Lingqu, Huawei built AI memory storage OceanStor M900, with I/O latency and first-token latency reduced by more than 50% compared with an L3.5-layer storage system interconnected by PCIe plus RoCE. Domestic computing power is evolving from single-point hardware competition into full-ecosystem confrontation across "chip-interconnect-storage-OS-ecosystem," and system-level high efficiency has become one of the core competitiveness factors.
Risk factors:
Global macroeconomic downturn; changes in the international political environment and intensifying trade frictions; downstream demand falling short of expectations; AI innovation falling short of expectations; AI commercialization progress falling short of expectations; domestic substitution progress falling short of expectations; domestic wafer fab expansion falling short of expectations; advanced process technology development falling short of expectations; intensifying competition among downstream manufacturers; risk of sharp increases in raw material prices caused by inflation; further tightening of U.S. sanctions against China; large fluctuations in exchange rates; technology iteration falling short of expectations; etc.
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