Open Source Securities: Huawei's Tao Law paper has been updated again, focusing on Fab, CP testing, and new devices.

Kinerja Securities published a research report stating that over the weekend, Huawei released a new paper titled Huaweis Tao Chips Should Have 'Melted Down', addressing the market's concerns about chip heat dissipation and power consumption with actual measurement data, analysis, and solutions. Under equivalent performance, the Kirin 2026 achieved a 66% reduction in NPU power consumption, 58% reduction in GPU consumption, and a 41% reduction in CPU performance core consumption; furthermore, the Tao chip can flexibly switch between power consumption and performance, showing significant computational power improvement when operating at full speed. The firm believes that Huawei's logic folding is more an innovation in design philosophy and pathways, rather than a one-time solution, suggesting that emphasis should be placed on Fab, CP testing, and new equipment phases. Key points from Kinerja Securities are as follows: 1. The Tao chip reduces power consumption while increasing density. In a typical SoC, the power consumption from data transmission (approximately 80%) surpasses that of the computing parts, while circuit folding shortens the connections in critical paths. Overall, through circuit folding, the typical core wire length is reduced by 20%, and critical path wire lengths are shortened by 70%, with the most power-consuming wiresclock buffersbeing halved. In addition, the increased number of transistors achieved through circuit folding can be used to build more parallel cores, allowing each core to operate at lower voltage and clock frequencies, providing greater flexibility. The end result shows that, compared to the previous generation of planar structure chips, the Kirin 2026 achieved a 66% reduction in NPU power consumption, a 58% reduction in GPU power consumption, and a 41% reduction in CPU performance core power consumption, with performance remaining unchanged. 2. The Tao chip can flexibly switch between power consumption and performance. This paper measured the performance of the Kirin 2026 in two types of scenarios, comparing it with the previous generation of chips: one ensured equivalent performance comparison efficiency, and the other ran the chip at full speed for performance comparison. Measurement data shows that compared to the Kirin 9030 Pro, the Kirin 2026's NPU, GPU, CPU P-core, DSP, and other modules can achieve lower frequencies, voltages, and power densities at the same performance level, while showing significantly improved performance at full speed, specifically: The NPU can achieve a frequency drop of 63% at the same 29 Tops computing power, with voltage dropping from 0.85V to 0.55V, power dropping 66%, and power density decreasing 73%, while achieving a 141% increase in computing power (141 Tops) at full speed. The GPU, operating at 61 FPS, has a voltage that is 200 mV lower, with power dropping 58%, and frame rates improving by 42% at full speed; the higher the modules parallelism and data requirements, the more significant the returns from Logic Folding technology. The DSP, under the same load, sees power drop by 25%, but power density increase by 24%, primarily due to area decreasing by 40%. The Kirin 2027 will address this issue, ensuring power density excels compared to planar designs, while power consumption decreases by 47%. CPU cores significantly benefit from circuit folding, achieving the HNX benchmark score of the 9030 Pro with a 9% lower clock frequency and a supply voltage lower by 200 mV, with the score for full-speed operation improving by 18%. 3. For localized high heat, Huawei believes that alternating the arrangement of high-heat and cooling modules can provide a solution. Chip failure primarily arises from localized high heat causing transistor junction temperatures to exceed operational limits. Huawei's solutions are twofold: first, reducing the source power density through folding to prevent localized high temperatures. Second, actively conducting thermal arrangements during design to place the modules generating the most heat in the positions where the heat dissipation paths are most effective to achieve balance. In summary, we believe that Huawei's logic folding is more of a design philosophy and pathway innovation, not merely presenting a one-size-fits-all solution but offering a new exploratory direction beyond traditional pathways. As stated at the end of the paper: In mythology, Sisyphus is punished to push a stone up a mountain, only to watch it roll back down, starting all over again. The engineering practice following the expansion law presents a similar rhythm: folding chips, striving for time margins, and investing them into power optimizationthen another generation of products emerges, and the boulder begins to roll again. 4. Investment recommendations: Focus on Fab, CP testing, and new equipment. Fab: Semiconductor Manufacturing International Corporation, Hua Hong Grace Semiconductor. The Tao law directly drives demand for advanced process wafers, and the design innovation of the Tao law mainly stems from the collaboration and research with upstream wafer fabs. (The original text states: We view hybrid bonding as a wafer-level, interlayer device manufacturing step rather than simply a packaging process. D2W bonding is essentially a bare die processing techniquethat is, pick and place. It has evolved from chip packaging factories. Its precision benchmark is relatively low, and even after years of optimization, it remains at the micrometer level. However, W2W bonding starts from another dimension: wafer manufacturing processes.) CP testing: Hangzhou Changchuan Technology, Maxone Semiconductor, Sidea Semiconductor Equipment. More wafers lead to more probe card needs, more prober demands, and more testing machine requirements; the business scale of the aforementioned three companies is positively correlated with the number of wafers. Equipment: Piotech Inc., Hwatsing Technology, Kingsemi Co., Ltd. The most critical process direction driven by the Tao law is ultra-fine pitch hybrid bonding. We understand that Piotech Inc. W2W equipment has already begun shipping in related processes, while Hwatsing Technology's thinning, CMP equipment, and Kingsemi Co., Ltd.s temporary bonding and debonding devices are expected to benefit.