Sinolink: Semiconductor Testing Value Reassessment, AI-Driven Related Equipment Moves Towards Structural Growth

Sinolink released a research report stating that semiconductor testing is a key process for ensuring chip performance, yield, and reliability, and that AI is driving the industry from traditional cyclical recovery to structural growth. According to SEMI's forecast, global semiconductor test equipment sales are expected to grow by 31.0% year-on-year to $15.3 billion by 2026 and reach $20.8 billion by 2028, with a compound annual growth rate of approximately 21% from 2025 to 2028. Among them, SoC testers will benefit from the expansion of high-end logic chips such as GPUs and ASICs, while memory testers will benefit from the increased stacking layers, interface speeds, and quality requirements of HBM. Meanwhile, the resurgence of capital expenditure among downstream assembly and testing factories and the intensive launch of advanced packaging projects are expected to continue releasing demand for testing machines, sorting machines, and interface components. The global high-end ATE market is highly concentrated, where competitive advantages have extended beyond individual machine parameters to include core platforms, customer validation, testing program ecosystems, mass production delivery, and Test Cell collaboration capabilities. The domestic testing equipment industry is expected to gradually move from breakthrough single products to platform-based expansion. Sinolink's main viewpoints are as follows: The expansion of AI infrastructure drives equipment demand from three dimensions: "more chips, more complex chips, and more testing." The expansion of AI servers and the development of self-researched ASICs by cloud vendors broaden the testing base for high-end logic chips; the shift from single die to multi-die systems, driven by Chiplets, HBM, and advanced packaging, increases the resource allocation for digital, memory, high-speed interface, and power testing; the addition of testing insertion points such as KGD, die-level testing, burn-in, and SLT, combined with extended single test times, requires customers to increase parallelism or invest in more equipment to maintain production rhythms. Testing shifts from a cost aspect to a key means of reducing the total cost of advanced packaging systems, and the value of testing per die is expected to increase. In multi-Chiplet packaging, undetected bad dies can lead to the overall scrap of other good dies, interposers, and subsequent packaging processes. While increasing testing coverage may raise testing costs, it can significantly lower the total system cost. As HBM stacking layers, die-to-die interconnects, high-speed interfaces, and packaging values increase, high-end testing platforms need to configure more channels, instrument boards, power supplies, and high-specification interface hardware, driving Test Cells from basic configurations to high-end configurations. Industry competition is expected to shift from fragmented single product competition to platform integration, with customer and platform accumulation determining long-term patterns. Advantest's development indicates that the competitiveness of testing equipment does not stem from breakthroughs in individual models but is formed by modular platforms, installation foundations, testing procedures, customer validation, scale delivery, and collaboration in adjacent processes. The firm believes that manufacturers with core testing platforms, sustained research and development capabilities, and mass production validation from leading customers are likely to evolve from niche product suppliers to comprehensive testing platforms, enhancing the value provided to individual customers through sorting, interfaces, aging, and system-level testing; in the long term, this may create a competitive landscape dominated by a few platform-based manufacturers with specialized equipment and interface manufacturers participating in a collaborative manner. Investment Recommendations The firm believes that the current boom in testing equipment is mainly driven by structural growth resulting from the expansion of AI servers, the ramp-up of HBM, and advanced packaging. The increase in the number of chips expands the testing base, and rising complexity drives upgrades in testing resources and Test Cell configurations; increases in testing insertion points and testing times further boost the demand for equipment capacity. It is recommended to focus on platform-based manufacturers that have established core testing platforms, possess validation and mass delivery capabilities from leading customers, and can extend into adjacent areas such as sorting machines, probe stations, SLT, and interface components; also, pay attention to specialized manufacturers that establish stable advantages in segmented fields such as analog and power testing while continuously expanding into high-end SoC, memory, and mixed-signal testing. Specifically, Hangzhou Changchuan Technology has the foundation to expand from digital SoC testing to a comprehensive Test Cell platform, Beijing Huafeng Test & Control Technology has deep accumulation in analog and power testing, while PowerTECH Co., Ltd. is expected to leverage its advantages in power testing to further expand its product boundaries. Risk Warnings Downstream AI infrastructure investments and capital expenditures by wafer fabs and assembly/test factories may fall short of expectations; development of high-end SoC, memory, and mixed-signal testing equipment or customer validation may progress more slowly than anticipated; intensified industry competition and platform expansion may dampen profitability; limitations in the supply of core components and risks of overseas export controls; high customer concentration and fluctuations in equipment acceptance and order release rhythms.