Sealand: The Advantages of AI ASIC Inference Scenarios are Remarkable, Establishing a New Landscape for Computing Power Together with GPUs

Sealand has published a research report stating that AI ASICs exhibit significant energy efficiency and cost advantages in inference scenarios, which is expected to accelerate their adoption among major internet companies. Meanwhile, the firm believes that other leading domestic chip manufacturers will form a long-term coexistence relationship with large internet firms' self-developed chips, benefiting top chip manufacturers and upstream and downstream enterprises in the internet AI ASIC industry chain that possess self-developed architecture and ecosystem synergy capabilities. Based on this, they maintain a "Recommended" rating for the computer industry. The main points from Sealand are as follows: Overview of AI ASIC: Significant advantages in inference scenarios, expected to coexist with GPUs in the long term. AI ASICs are chips custom-designed for neural network training and inference tasks. By removing general-purpose redundant modules and introducing pulse arrays/specialized tensor units, they achieve higher computational density, superior energy efficiency, and lower costs, and can be categorized into architectures such as TPU, NPU, and LPU. According to Semiconductor Industry Insights, over 90% of AI frameworks natively support Nvidia CUDA in training scenarios, but the model algorithm logic in inference scenarios is relatively fixed, requiring lower flexibility from the chips while being more sensitive to energy efficiency and costs, highlighting the advantages of AI ASICs. Global cloud leaders and model manufacturers are generally exploring AI ASIC solutions. According to DIGITIMES Research, global shipments of high-end AI ASICs are expected to reach 7.23 million units by 2026, with a year-on-year growth rate exceeding 40%. Counterpoint Research estimates that shipments in 2027 will triple compared to 2024. In terms of the industry chain, the cooperation model for AI ASICs is typically joint development, where large firms are responsible for defining chip specifications and architectural design, while the physical implementation is jointly completed with professional ASIC design companies like Broadcom, Marvell, WorldChip, and MediaTek. Broadcom and Marvell occupy key positions due to their critical IP and system solutions. AI ASICs and GPUs do not replace each other but represent a trade-off between "efficiency" and "flexibility." A multi-chip strategy has become standard; according to TrendForce, AI ASIC server shipments are expected to account for 27.8% of the total AI server market by 2026, increasing to 39.5% by 2030. Overseas AI ASIC: North American CSPs have undergone multiple iterations and have begun mass deployment. Google's TPU currently features the seventh generation Ironwood (TPU v7), achieving a single chip FP8 dense computing power of 4.6 PFLOPS, equipped with 192 GB HBM3E; the eighth generation TPU (split into 8t/8i) was released in April 2026, with mass production expected by the end of 2027. DIGITIMES Research projects that Google TPU shipments are expected to reach 3.326 million units in 2026, accounting for 46% of the overall AI ASIC market. According to Wall Street reports, AWS Trainium 3 has entered the shipping ramp-up phase, with a single chip FP8 computing power of 2.52 PFLOPS, expected to see volume production starting in Q3 2026, with an annual shipment of around 1.47 million units; Trainium 4 is expected to be released in December 2026, with a single chip FP8 dense computing power increased to 7.6 PFLOPS. Meta disclosed a four-generation chip roadmap (MTIA 300/400/450/500) over two years, covering FP8 computing power from 1.2 PFLOPS to 10 PFLOPS, with MITA 450 and 500 planned for large-scale deployment in 2027. Microsoft's Maia 200 was released in February 2026, optimized for inference scenarios, with FP4 and FP8 computing power of 10.15 PFLOPS and 5.07 PFLOPS, respectively, used in Azure data centers, capable of supporting applications like OpenAI GPT-5.2. Domestic AI ASIC: Domestic CSPs have all made layouts, aiming to support some AI cloud computing power demands. ByteDance's self-developed chip logic lies in lowering computing power costs through custom chips, covering four product lines: AI chips/CPU/VPU/DPU. The AI inference chip SeedChip adopts an NPU architecture, with mass production expected to yield 100,000 units in 2026, with long-term capacity planning ramping up to 350,000 units, mainly applied in its own business scenarios like Douyin and Doubao; they are also developing a new generation of inference chips inspired by Groq LPU, incorporating RRAM resistive random-access memory technology to circumvent HBM supply bottlenecks. Ali's Pingtouge covers AI chips, server CPUs, and other three product lines, with the Zhenwu 810E (PPU) following the GPGPU route, matching Nvidia's H20 in comprehensive performance, already deployed in multiple ten-thousand card clusters on Alibaba Cloud; the next-generation Zhenwu M890 training and inference integrated chip is set to launch in May 2026, expected to improve performance by about three times compared to the 810E while also releasing the 128-card Panjiu ultra-node solution. As of May 2026, cumulative shipments of AI chips reached 560,000, serving hundreds of customers across over 20 industries. Baidu's Kunlun chip has completed three generations of iterations based on its self-developed XPU architecture, with the main product P800 utilizing a 7nm process, having been delivered to multiple ten-thousand card clusters; the M100, aimed at cloud-scale inference, is set to launch in July 2026, competing with Nvidia's H20; the M300 is positioned as a chip for ultra-large-scale multimodal model training, expected to hit the market in early 2027. Kunlun has started guidance for its listing on the Sci-Tech Innovation Board, while simultaneously advancing an A+H dual-market listing strategy. Tencent is engaged in AI inference/video transcoding/network ASIC sectors, jointly developing the Zixiao series of AI inference chips with Suirian, with Zixiao 1.0 already in mass production and deployed in multiple leading Tencent Cloud businesses; Zixiao 2.0, aimed at large model training and inference, will be released in July 2026, with training performance improved by four times and inference throughput enhanced by three times. Tencent plans to increase the proportion of self-developed Zixiao chips to 30% by 2026, with deployment scales expanded to the level of 100,000 cards; at the same time, Tencent is supplementing computing power through direct procurement from Suirian, with procurement totaling 830 million yuan in 2025, accounting for over 80% of Suirian's revenue. Risk Warning: The risks include weaker-than-expected recovery in downstream industry demand, slower-than-expected development of large AI models, fluctuations in raw material prices, intensified market competition, fluctuations in exchange rates, and key focus on companies underperforming expectations, as not all products are fully comparable; relevant materials and data are for reference only.