Is Tower Semiconductor (TSEM.US) undervalued? Wedbush says silicon photonics expansion will open up growth opportunities in AI infrastructure.

The latest research report issued by the well-known investment firm Wedbush Securities on Wall Street shows that Tower Semiconductor (TSEM.US), a leading semiconductor manufacturing and wafer foundry company based in Israel, has announced a large-scale expansion of its large semiconductor factory in Uozu, Japan. This expansion will greatly help the company achieve its somewhat conservative performance outlook. "Given that TSEM has previously announced plans to expand its Uozu large semiconductor factory - we believe this will roughly double TSEM's silicon photon chip production capacity, reaching about $1 billion per quarter - we believe that buyer investment firms and at least some top-selling research institutions have adjusted their forecasts to include additional revenue expectations," wrote Matt Bryson, a senior analyst at Wedbush, in a report to clients. "For example, our latest forecast for 2028 is slightly higher than the company's updated performance guidance. Nevertheless, TSEM's outlook still appears conservative as it assumes that the capacity utilization rate of high-performance optical products in 2028 will be only about 60%, creating favorable conditions for TSEM to surpass revised expectations. Furthermore, we believe that TSEM expects to start production of more capacity in 2029 that will bring strong incremental revenue, which is new and additional information. Overall, we believe this news is significantly positive for the company's fundamentals and its stock." Tower Semiconductor (TSEM) will invest approximately $3 billion to expand its 300mm large wafer factory in Uozu, Japan. The factory is expected to support production of 300mm silicon photon and silicon germanium related chips, as well as support cutting-edge advanced packaging business. The first production line in the dual-track expansion plan is expected to be ready for production in the fourth quarter of 2027. With this expansion, Tower Semiconductor has raised its 2028 performance outlook to revenue of $3.6 billion and a new operating profit of $1.2 billion, previously expected to be $2.8 billion and $750 million, respectively. While not competing with Taiwan Semiconductor Manufacturing Co., Ltd. Sponsored ADR for advanced processes, Tower Semiconductor is positioned in the AI data flood. Tower Semiconductor (TSEM) is an Israel-based specialty analog semiconductor wafer foundry, not core to Taiwan Semiconductor Manufacturing Co., Ltd. Sponsored ADR, focused on customer-specific intellectual property platforms, including silicon photonics (SiPho), silicon germanium (SiGe), RF SOI, RF CMOS, high-performance analog, power management, image sensors, mixed-signal chips, and MEMS. It serves over 300 customers in communication infrastructure, automotive, industrial, medical, consumer electronics, aerospace, and defense markets. Tower Semiconductor's business moat comes more from process intellectual property, customer certification cycle, and unique capacity scarcity, rather than relying solely on transistor size leadership. The core purpose of this expansion in Japan focuses on strengthening 300mm silicon photonics, silicon germanium, and advanced optical packaging capabilities. The first expansion path will convert the existing Niigata factory into a 300mm silicon photonics and advanced optical packaging base, supporting Uozu Fab 7, expected to be fully ready for production in the fourth quarter of 2027; the second path is to build a new 300mm factory near Fab 7, aiming to significantly increase the capacity of silicon photonics and silicon germanium, starting to make a significant incremental contribution from 2029. The company's latest filing shows that the project could reach up to $30 billion in scale and has obtained $1 billion in support from the Japanese government. In terms of specific semiconductor manufacturing and wafer foundry strategy, this is a key expansion for Tower Semiconductor as it upgrades itself from a traditional analog foundry to an artificial intelligence data center optical interconnect infrastructure supplier. As GPU cluster scales up, system bottlenecks are shifting from single-chip computing power to chip-to-chip bandwidth, network power consumption, and optoelectronic conversion efficiency; silicon photonics is responsible for high-speed optical transmission, silicon germanium is suitable for high-speed, low-noise analog and RF devices, and advanced optical packaging determines whether optical chips, laser diodes, and electronic chips can be densely integrated. Tower Semiconductor has used the silicon photon platform for 1.6T data center optical modules and clearly aimed at artificial intelligence infrastructure and next-generation optical networks. On the investment level of the specific AI computing industry chain, this makes it a high-growth and elastic "optical interconnect seller" in the AI computing chain, but the return on investment still depends on customer order realization, capacity ramp-up, and utilization rates, and cannot be inferred that profits will increase in sync with the $30 billion capital expenditure alone. As Moore's Law fades from view, silicon photonics breaks through the "copper wall", and advanced packaging rewrites the value chain of computing chips. The underlying bottleneck of artificial intelligence is shifting from the number of transistors on a single chip to data transport capacity. Large-scale model training and inference require thousands or even larger-scale accelerators to work together, but data transmission between GPUs and HBMs, chips and chips, and cabinets and cabinets is constrained by increasing copper interconnect distance, signal integrity, bandwidth density, and power consumption. When the energy consumed by data movement approaches or exceeds the computation itself, shrinking the process independently can no longer solve the system efficiency problem. Silicon photonics uses light instead of high-speed electrical signal transmission and places optical engines near switch chips or computing chips through co-packaging optics to shorten signal paths, increase bandwidth density, and reduce power consumption per bit. AI chip leader NVIDIA Corporation has positioned co-packaged optics as a crucial extension of its million-scale GPU artificial intelligence factory. Network-1 Technologies, Inc., its Spectrum-X photon switch, claims to provide 1.6Tbps per port bandwidth, approximately 3.5 times energy efficiency improvement, and 10 times network resilience, showing that "optical interconnect" is evolving from a communication device upgrade to a core infrastructure determining the effective computing power of clusters. Advanced packaging is no longer just the "outer shell" in chip manufacturing but a system-level architecture platform that extends Moore's Law: it can break through the single-wafer mask size and yield limitations, tightly integrate CPUs, GPUs, I/O chips, analog devices, and multi-stack HBMs from different processes in a 2.5D or 3D manner to build a "supercomputer inside the package" with lower latency, higher bandwidth, and better cost. Taiwan Semiconductor Manufacturing Co., Ltd. Sponsored ADR's CoWoS is responsible for integrating logic chips with HBM, with its 5.5 times larger CoWoS-L mask plan expected to be certified by 2026, and larger-scale platforms are also in progress; at the same time, COUPE technology integrates silicon photonics with electronic control chips through SoIC, and further introduces CoWoS co-packaged optics, indicating that advanced packaging and silicon photonics will eventually converge into an integrated "compute-store-network" platform. For investors, the next phase of AI semiconductor excess alpha returns will not only come from advanced processes but will also spread to core areas of the AI computing industry chain, such as CoWoS and 3D packaging, silicon photonics wafer foundry, optical engines and lasers, HBM/DRAM/NAND storage chips, packaging substrates, hybrid bonding, testing, and liquid cooling. The true moat of chip manufacturing giants will be mass production yield, customer certification, system collaborative design, and capacity delivery capabilities, rather than just owning a certain concept technology.