Huachuang Securities: The Tao Principle Promotes the Shift of Semiconductor Towards Design Methodology, Domestic EDA Faces Value Reevaluation.

Huachuang Securities released a research report stating that on May 25, 2026, at the IEEE International Symposium on Circuits and Systems (ISCAS 2026) held in Shanghai, Huawei presented the "Tao () Law", proposing to replace "geometric scaling" with "time () scaling", continuously compressing signal propagation delay and increasing transistor density through innovative technologies such as logic folding, exploring a new path for the continuous evolution of semiconductor and electronic systems. The Tao Law promotes the evolution of semiconductors from process scaling to design methodology, full-stack collaboration, and manufacturing data feedback loop. Domestic EDA, as a core industrial software base connecting chip design, manufacturing, packaging, and system optimization, is expected to continuously increase in strategic value. Huachuang Securities' main points are as follows: After the process dividend slows down, design collaboration becomes the new main line of semiconductors. Huawei proposed the Tao () Law, which essentially broadens the evolution of semiconductors from simple reliance on geometric process scaling to comprehensive optimization involving time constants, signal propagation delay, and system performance. Huawei pointed out that in recent years, Moore's Law, which has dominated the semiconductor industry for over half a century, is facing dual challenges of physical limits and economic benefits, with the slowing of transistor geometric scaling and the diminishing cost benefit of transistors becoming common issues in the industry. Huawei revealed that the Tao Law constructs a multi-level collaborative optimization system spanning devices, circuits, chips, and systems. At the circuit level, logic folding breaks through traditional planar layout physical boundaries, shortens critical path wire lengths, and reduces signal propagation resistance and capacitance loads. The securities firm believes that the core contradiction of the semiconductor industry may shift from "can the process continue to shrink" to "can existing process and system architecture potential be released using EDA and design methodologies". Full-stack collaboration requirements to improve, EDA toolchain undergoes system upgrade. The Tao Law emphasizes the full-stack software/hardware core collaboration design of "software, architecture, and chips", and at the system level, it reconstructs the computing system interconnect protocol through the agile bus to reduce system communication delays. In the context of the EDA process, this means that the toolchain needs to embed further into key processes such as device modeling, PDK construction, circuit simulation, parasitic parameter extraction, timing power consumption analysis, physical verification, advanced packaging, and system-level collaboration optimization. Empyrean Technology's official website shows that its EDA products cover complete custom design platforms, digital circuit design, wafer manufacturing, advanced packaging, and 3DIC design directions, aligning with the industry trend of complex chip design moving from single-point tools to full-process platforms. The securities firm believes that the Tao Law is expected to drive domestic EDA from "point tool replacement" to "full-process, cross-level, strong collaboration" industrial software base. Mass production verification opens up space, domestic EDA transitions from substitution to innovation. Huawei mentioned that over the past six years, 381 chips have been designed and mass-produced based on the Tao Law, with the Kirin chip set to be unveiled in the fall of 2026 being the first to adopt logic folding technology, significantly improving performance. Unlike pure concept releases, the mass production of 381 chips indicates that this path has entered the engineering verification stage. The significance for the EDA industry is that new architectures, methods, and design constraints will bring about a large number of localization tool adaptations, design manufacturing collaboration, and system-level verification requirements. The State Council's policy explicitly states that the integrated circuit industry and software industry are at the core of the information industry and proposes further optimizing the industry development environment, enhancing industry innovation capabilities and development quality. The policy in Shanghai also proposes the implementation of a special action plan for EDA ecosystem construction, supporting breakthroughs in full-process EDA tools, the construction of EDA open cloud platforms, and the procurement of autonomous and secure EDA tools. The securities firm believes that domestic EDA is poised to transition from "overseas tool substitution" to "collaborative innovation oriented towards domestic processes, domestic architectures, and domestic systems", with platform manufacturers possessing the capabilities of process collaboration, manufacturing data feedback loops, and customer ecosystem positioning likely to benefit first. Risk warning: slow progress in the engineering development of the new semiconductor path, domestic EDA product verification and customer adoption falling short of expectations, fluctuations in downstream wafer fabs and chip design capital expenditure, and risks related to international trade environment and supply chain disruptions.