Glass, revolution chip?

Over the past half century, humans have been obsessed with making things "smaller." This has been the only way to integrate more transistors onto a single chip. Shrinking transistors to 10 nanometers, 5 nanometers, and 3 nanometers is the definition of semiconductor technology. But in the end, physical laws have given a cold judgment: "You can't shrink anymore." In response to this, people changed their thinking. "If we can't shrink the size of individual units, why not combine several units to build something bigger?" This question changed the rules of the game. Today, the core focus is no longer on the microcircuits inside the chip, but on the "bridges" connecting the chips and the "ground" supporting them. The nanometer-scale war is over, and the micrometer-scale war has begun. And in the center of this battlefield stands a piece of transparent glass. Why chips can't get any bigger As artificial intelligence models grow larger, the number of transistors that need to be integrated onto a chip also increases. To accommodate more transistors, the size of the chip must increase - but there is a limit to how large a chip can be. The circuit patterns on a chip are formed using photolithography, and the area that can be covered in a single exposure is limited. This is the area limit of the lithographic mask - currently, it is approximately 858 square millimeters. NVIDIA's GH100 chip already has an area of 814 square millimeters, almost touching this limit. But aside from size, there is another problem. Imagine drawing a grid on a large canvas. Each square represents a color block. Now dip a small paintbrush in pigment and flick it on the canvas. Each square that the pigment drips into will have a flaw. If the squares are small, many color blocks remain intact. But what if the squares are larger? If just a drop of pigment falls on a square, the entire square will be ruined. The larger the square, the faster the number of intact color blocks decreases. This is the yield issue. You can't get any smaller, but you can't get any larger. Single-chip chips are a dead end. So, the industry's response is to go in the opposite direction. Separate, then reconnect Imagine using a 3D printer to print a Hogwarts Castle in one go. If there is an error during the printing process, the whole piece will have to be discarded. But what if you build it using LEGO blocks? If one block is faulty, you can just replace it. Chiplet is like LEGO bricks. It breaks down a huge chip into smaller components, manufactures them separately, and then puts them back together. Smaller chips have higher yields, naturally reducing costs. They are not constrained by lithographic processes. More importantly, each Chiplet can use different process nodes - advanced 3nm processes for computing cores, and lower-cost 6nm processes for I/O circuits. Just like how marble is placed in the living room and bricks are stacked in the warehouse, this is the rational choice. NVIDIA's Blackwell encapsulates two chips near the limit into a single GPU. Intel's Ponte Vecchio assembles 47 chips into one processor. But this comes at a heavy cost. Within a single chip, all components are connected via internal traces - fast, wide coverage, low power consumption. Once the chip is split apart, the communication that was originally done inside the chip must be moved outside the chip. It's like a team that used to have meetings face-to-face in the same building but suddenly got split up into different offices and now has to video call each other. The quality of video calls determines the efficiency of the entire team. If the connection speed between chips is not as fast as the internal traces they replace, there is no point in splitting them up. Just producing good chips is no longer enough. This era belongs to those who can connect them. Bacon, Eggs, and McGriddle (CoWoS) The structure of stitching small potato chips together looks like a McGriddle - just missing the bread on top. The bottom British muffin-like structure is the substrate, which supports the entire component. It provides power to the chips, connects them to the outside world, and securely holds the entire package together. The bacon on top is the chips - GPU, HBM memory, and the actual computing components. In the past, when there was only one chip, you just needed to put the bacon on the muffin and you were done. But in the chip era, the bacon slices need to communicate with each other. So, a layer of egg yolk is inserted between the muffin and the bacon - the middle layer, a bridge that can connect the chips at high speed. You might have heard of the abbreviation CoWoS. It stands for Chip-on-Wafer-on-Substrate. The name describes the structure. The key issue in this architecture ultimately comes down to one thing: what material should be used to make the egg and muffin? This decision determines the performance, cost, and how many AI chips can actually be produced globally. The 25-year dominance of organic substrates To understand this story correctly, you need to know who the king was at the time. Today, the majority of substrates are made of organic materials - stacked layers of resin and fiberglass. They are stable and inexpensive. Since replacing ceramic substrates at the end of the 1990s, organic substrates have quietly become the cornerstone of the semiconductor industry for 25 years. Twenty-five years is long enough for almost everything to change. During this time, the size of transistors has shrunk from several hundred nanometers to 3 nanometers, and the computing power of chips has increased exponentially. But what about the substrate? It has quietly continued to work on the same base material. Artificial intelligence has disrupted this tranquility. To understand the problem, you need to understand the two tests that high-quality substrates must pass. Test one: withstand high temperatures. All materials expand when heated. When artificial intelligence accelerators consume hundreds of watts of power and heat up, the chip (silicon) and its substrate below will expand - but at different rates. This is similar to two people with different strides participating in a three-legged race. The difference in expansion rates is called the coefficient of thermal expansion (CTE). The expansion rate of organic substrates is six to seven times that of silicon. For small packages, this difference can be negligible. But when the package size reaches the level of artificial intelligence chips, this warpage becomes very serious. In the worst-case scenario, solder joints will crack. Test two: signal protection. When electrical signals pass through the substrate, the substrate material absorbs signal energy. Imagine driving a car on a dirt road. It's fine at low speeds. But the ultra-high-frequency signals needed for artificial intelligence chips become blurry and hard to distinguish. Recovering the blurry signal forces the digital signal processor (DSP) to work overtime, consuming power and generating heat, which further degrades signal quality - creating a vicious cycle. Organic substrates have passed these two tests with flying colors over the past 25 years. The small form factor, the slow speed. But when faced with AI chips, these two tests have failed simultaneously. Glass poses a challenge Organic substrates are inexpensive, but they have encountered bottlenecks in the field of artificial intelligence chips. Silicon intermediate layers have excellent performance, but consume a large amount of packaging resources and are difficult to scale. Between them lies a blank space. This is where glass comes into play. "Glass substrates" is a general term, but there are two completely different paths in reality. Option one: Replace the intermediate layer with glass. Instead of using silicon, which is used on the display industry's large glass processing equipment, to build the bridging layer that was originally occupied by silicon. To use a McDonald's McMuffin analogy, it's like using an ingredient that doesn't need to be heated instead of an egg. The freed up heating equipment means you can make more bacon (potato chips). Samsung's goal is to achieve this by 2028. The second path is to replace the substrate with glass. This is a completely different approach - fundamentally addressing the performance bottlenecks of organic substrates. While more expensive than organic substrates, it is worth the cost. Intel has invested over $1 billion in this direction. While both are referred to as "glass," they are working on different problems. Glass can challenge this because it has overwhelmingly favorable results in both tests where organic substrates have failed. The coefficient of thermal expansion of organic substrates ranges from 17-20 ppm/C. Silicon, on the other hand, is about 3 ppm/C. The difference between the two is six to seven times. Glass composition can be adjusted to near 3 ppm/C, which means it can match the thermal expansion coefficient of silicon. This is the most fundamental advantage. The packaging size that cannot be achieved on organic substrates becomes possible on glass. If you think organic substrates are like a muddy road, then glass is like a newly paved asphalt road. Signal loss in glass is more than ten times lower than that in organic substrates. Less signal loss means lighter load on the signal recovery circuit, lower power consumption, and less heat production, thus breaking the vicious cycle. But aside from these two important points, glass also has two characteristics that organic substrates can never replicate. Its surface is extremely smooth. If the surface of an organic substrate is like a muddy road, then the glass surface is like an ice rink. Hybrid bonding - an emerging technology that can directly bond copper pads without solder - relies on this smoothness. It can reduce the spacing between connection points from tens of micrometers to less than 10 micrometers in the same area, achieving tens of times more connections. This is not possible on organic substrates but is achievable on glass. Glass is transparent, allowing light to pass through it, which means optical waveguides can be embedded directly into the substrate. More importantly, with the rise of optical interconnect technology, the application has expanded from just the chip surface to the inside of the substrate. In this world, an electrical signal can be converted into an optical signal, and transmit between chips - and glass is the foundation material for constructing this world. Glass faces "three major mountains" Of course, if glass were truly universal, it would have taken the lead long ago. First and foremost, the fundamental issue is that glass can break. During cutting, drilling, and handling processes, micro-cracks can form on the glass surface. These cracks can quickly expand when the chips undergo tens of thousands of power cycles (each cycle causes expansion and contraction), leading to catastrophic consequences. Laboratories are working on suppressing these cracks through edge finishing techniques and reinforcement measures, but there is still a lack of long-term reliability data for thousands of thermal cycles. Glass's thermal conductivity is two orders of magnitude lower than silicon. Silicon's thermal conductivity is about 130-150 W/mK, while glass is around 1 W/mK. However, this weakness also brings an interesting turn of events. Keeping in mind the transparency of glass - if optical waveguides are embedded in the substrate, data transmitted as light would hardly produce any heat as it passes through the substrate. A low thermal conductivity is no longer a fatal flaw. Glass's weakness is complemented by the advantages of optical interconnections. There is another paradox here. While glass does not absorb signals, its properties lead to an unexpected weakness in power supplies. In a noisy caf, the neighboring conversation will be drowned out in the background noise; but in an empty concert hall, a cough will echo in all directions. Glass substrates are like that empty concert hall. Instead of absorbing the small noise generated by power circuits, glass substrates reflect it, leading to power fluctuations instead of smooth transmission. Reliability, heat dissipation, and power supply noise - glass faces three formidable barriers. Laboratories have demonstrated the potential of glass, but heavy obstacles remain to be overcome before mass production can be achieved. However, it is certain that the sharp blade used to cut transistors has been dulled. Instead, the needle and thread used to connect chips are becoming sharper. Substrates are no longer just simple plastic bases; they are becoming giant circuits - the second semiconductor determining the performance limit of the entire system. By 2028, glass will become the core component of cutting-edge artificial intelligence accelerators. Furthermore, light can pass through glass, allowing optical signals to be converted from electrical signals and transmitted between chips - a whole new world awaits us to explore. Possibilities have been confirmed. Yet, amidst the laboratory's glass walls and production lines, there are still many hurdles to overcome. To overcome these obstacles, trillions of won are currently pouring in. The battle has just begun. Glass has the edge in matching thermal expansion coefficients and high-frequency signal properties. However, in applications with fine pitch requirements, it still lags far behind silicon. Its mass production yield is much lower than that of organic substrates, and its cost is several times higher. With limited public production data, it is difficult to determine exact numbers, but the industry's consensus is clear: the economic gap remains too large. However, the most critical difference lies in the necessity for glass and the uncertainty regarding whether it will actually solve the key issue at hand. Given the outcomes of the tests, one may jump to the conclusion that one material will win over the other; however, the reality is far from that straightforward. These tests and developments are not simply about performance and technical advantages, but also about brutal production yields, relentless standardization battles, and strategic considerations from companies like Intel. If glass were to secure a major purchase order, if AMD's certification process goes through, if Samsung's new generation of prototype machines produces positive results - only then will the fog on the battlefield lift. Until then, it's essential to analyze the signals at this crossroads carefully and decipher the future they signify. At this crossroads, the key isn't about prematurely predicting winners and losers. Rather, it's about interpreting the signals at the turning point. The signals to watch out for are: Absolics' first purchase order, Samsung's accreditation threshold, Samsung displaying the next-generation prototype machine, VisEra's panel pilot project, breakthroughs in ABF technology, and advancements in PCB small pitch technology. Connecting these scattered data points and extracting crucial information is the only strategic way to navigate the uncertain battlefield. The fog will eventually lift. When it does, the world will split - some will have hugged their secure positions while others are still searching for direction.