Open-source securities: Recent advances in storage computing technology have become the new mainstream for improving chip performance in the AI era.

Open Source Securities released a research report stating that with the continuous increase in AI computing power demand, the traditional von Neumann architecture faces a storage-computing performance mismatch issue. As a solution, near-storage computing technology has emerged, effectively integrating computing and storage through 2.5D and 3D stacking technologies, significantly improving memory bandwidth and reducing access latency. The institution believes that near-storage computing is expected to become a key trend in future technological development, particularly showing huge potential in high-performance computing and edge devices. Among them, HBM and CUBE solutions, as representatives, are gradually leading the industry transformation. Beneficiaries include Ingenic Semiconductor (300223.SZ), GigaDevice Semiconductor Inc.(603986.SH), and Rockchip Electronics(603893.SH). The main points of Open Source Securities are as follows: The increasing demand for computing power leads to a mismatch between storage and computing performance in the von Neumann architecture, and near-storage computing will break through this issue The von Neumann architecture focuses on computation, with computing and storage separated and working together to access and process data. In the AI era, as computing power continues to increase, the performance mismatch between storage and computing becomes evident. Near-storage computing utilizes advanced packaging technologies to package the computing logic chip and memory together, reducing the paths between memory and processing units to achieve high I/O density, thereby achieving high memory bandwidth and lower access costs. The firm believes that near-storage computing will become the mainstream solution for improving chip performance in the AI era. After multiple iterations, HBM has become the mainstream near-storage computing architecture for high-performance computing and data centers HBM uses TSV technology to stack DRAM dies to significantly increase I/O counts, combined with advanced 2.5D packaging processes, to achieve a more significant total channel width increase while maintaining low memory frequencies, with high bandwidth, high capacity, and low power consumption. Since 2016, HBM (High Bandwidth Memory) technology has been continuously innovating. HBM2 (2018) uses 8 layers of DRAM, providing 256GB/s bandwidth, 2.4Gbps transfer speed, and 8GB memory. HBM2E (2020) has increased the transfer speed to 3.6Gbps and the memory to 16GB. HBM3 (2022) will increase the stacking layers and managing channels, with a transfer speed of up to 819GB/s and 16GB memory. HBM3E will have a transfer speed of up to 8Gbps and a capacity increase to 24GB. Currently, HBM is widely used in high-performance computing, data centers, and other fields. As AI end terminals continue to land, the CUBE solution is expected to shine The CUBE solution adopts 2.5D or 3D packaging, integrated with the main SoC chip, achieving ultra-high bandwidth through up to 1024 I/Os, suitable for wearable devices, edge server devices, monitoring devices, and advanced applications such as Siasun Robot & Automation. CUBE has a relatively small capacity, suitable for edge applications. For example, in an AI-ISP, many gray areas belong to the neural network processor (NPU), and if the AI-ISP needs to achieve high computing power, it requires high bandwidth or SPRAM. However, using SPRAM on the AI-ISP is costly, and using LPDDR4 is also expensive as it requires 4-8 chips. Using the CUBE solution can reduce L3 cache, enlarge L4 cache, and reduce chip costs while increasing bandwidth. With the development of new AI end devices such as AI smartphones and Siasun Robot & Automation, CUBE is expected to become the mainstream near-storage computing architecture for edge AI. Risk warning: downstream demand falls short of expectations, technical verification and iteration fall short of expectations.